1. Field of the Invention
This invention relates to a Schmitt trigger circuit comprising inverters employing MOS field effect transistors (hereinafter referred to as MOS FET's).
2. Description of the Prior Art
When an input signal having slow rise and fall times is applied to a logic circuit, chattering may occur at the input stage. In order to prevent the chattering, the input signal is given to the logic circuit through the so-called Schmitt trigger circuit having hysteresis characteristics.
As the Schmitt trigger circuit, use has been made of the circuit shown in FIG. 1 wherein inverters 10 and 11 are connected in series between input and output terminals 13 and 14 and the output of the inverter 11 is fed back to the input of the inverter 11 through another inverter 12. The electric potential at the output point of the inverter 10 is determined by that at the output point of the inverter 12. The turn-off level V.sub.IL at the input terminal 13 is the value at which the voltage of the output terminal 14 changes from high to low levels; it is the value which can force the output of the inverter 12 to change from low to high levels with the output of the inverter 10. Similarly, the turn-on level V.sub.IH at the input terminal 13 is what can force the output of the inverter 12 to change from high to low levels with the output of the inverter 10. Since these values of the turn-off level V.sub.IL and the turn-on level V.sub.IH are different, the circuit in FIG. 1 operates as a Schmitt trigger circuit.
The turn-off and turn-on levels V.sub.IL and V.sub.IH are determined by the output impedances of the inverters 10, 12. In more detail, when the output impedance of the inverter 10 becomes smaller than that of the inverter 12, the output at the output terminal 14 turns to high or low level. Those output impedances depend on the characteristics of transistors constituting the inverters 10, 12 which have an inevitable manufacturing error. This makes it hard to control the turn-off and turn-on levels V.sub.IL and V.sub.IH.
Since each of the inverters 10, 11 and 12 is of the so-called CMOS type with a circuit formed of P-channel and N-channel type MOS FETs connected in series between power supply terminals, the power consumed in the Schmitt trigger circuit is very small. If, however, the output impedance of the N-channel type MOS FET (or P-channel type MOS FET) of the inverter 10 is not small sufficient to force the output of the inverter 12 to change, the circuit in FIG. 1 will no longer operate as a Schmitt trigger circuit. If the output impedance of the inverter 12 is not large compared to that of the inverter 10, the same maloperation will occur. These phenomena may be derived from manufacturing errors during the process of manufacturing transistors or otherwise caused when the circuit is exposed to gamma (.gamma.) rays as in the case of its use in an earth satellite.